1. Technical Field
The present invention relates in general to integrated circuitry and, in particular, to capacitors and their fabrication.
2. Description of the Related Art
Precision capacitors for complementary metal oxide semiconductor (CMOS) analog applications are generally metal-insulator-metal (MIM) capacitors or polysilicon-insulator-polysilicon (P-P) capacitors. P-P capacitors are becoming less popular, however, because of the problems connected with their use in conjunction with complementary metal oxide semiconductor (CMOS) technologies. More specifically, P-P capacitors are generally fabricated before CMOS structures, and the heat and oxidation cycles of the CMOS fabrication process degrade P-P capacitors. In addition, as analog circuits become more sophisticated, the allowed variation in the capacitance decreases and is preferably maintained at approximately 50 ppM/V. Because P-P capacitors suffer from carrier depletion (which changes the capacitance) as surface voltage across the P-P capacitor changes, P-P capacitors do not maintain the linearity required in sophisticated analog circuits. Further, P-P capacitors often trap charge within the dielectric during their use.
As a result, MIM capacitors, which are usually formed after the CMOS fabrication process, are becoming more popular for analog circuits. However, MIM capacitors also present manufacturing challenges, especially when used with copper wiring, because copper generally cannot be used as an electrode with an SiO2 dielectric layer. In particular, the present invention recognizes that the etching step(s) utilized to define the simplest MIM capacitor that does not use the underlying damascene metallurgy as an electrode etches the top and bottom plates and the dielectric in one step, and in doing so, creates contamination on the edge of the dielectric that contacts both plates. This contamination is not easy to remove and causes undesirable leakage between the top and bottom plates.
In view of the foregoing, the present invention provides an improved capacitor structure and method of fabricating a capacitor structure that prevents a contamination layer formed during etching from connecting the top and bottom plates and thereby causing leakage.
A capacitor structure in accordance with the present invention includes a bottom plate, a top plate, and a dielectric layer between the bottom and top plates. In addition, at least one insulating sidewall spacer that protects the dielectric layer during processing is formed along the perimeter of the top plate and overlaying a portion of the dielectric layer. In a preferred embodiment, the sidewall spacer, which may be an oxide insulator, is formed following an etch of the top plate to expose the dielectric layer.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.